1. Field of the Invention
The present invention relates to the simulation of circuit designs and, more particularly, to increasing the accuracy of timing analysis with respect to circuit designs.
2. Description of the Related Art
The operational speed of modern circuit designs has continually increased. This increase in speed requires highly accurate techniques for conducting timing analysis so that the designs can be adequately tested and verified. Typically, this sort of testing is performed using an Electronic Design Automation (EDA) tool. The EDA tool essentially analyzes a circuit design, which can be expressed using a hardware description language, as well as a timing description of the circuit design.
While the timing description of the circuit design may be expressed using any of a variety of different formats, one common way of expressing this data is through a Standard Delay Format (SDF) file. The Standard Delay Format Specification is available to developers from Open Verilog International. In general, an SDF file stores timing data for a circuit design. The data in the SDF file can represent design parameters including, but not limited to, delays, timing checks such as setup, hold, recovery, removal, skew, width, and period, timing constraints, as well as conditional and unconditional module path delays. This data is represented in a design tool-independent manner and, as such, can be used by a variety of different EDA tools.
SDF files have become an industry standard in terms of representing delay information for circuit designs. Still, there are disadvantages in the way that data from SDF files is used when computing various timing related quantities. More particularly, the SDF file format specifies that only one delay for each path is to be annotated for a given functional timing simulation. In illustration, an SDF file can include delay constructs that specify the minimum, typical, and maximum path delays for components of a circuit design. Presently, these values are not utilized simultaneously within a given functional timing simulation. That is, when a particular timing analysis is performed, such as setup or hold verification for example, either all maximum path delays or all minimum path delays are used for each component. This can lead to situations in which erroneous or overly optimistic timing analysis is performed on the circuit design.
It would be beneficial to perform various timing analysis operations for circuit designs in a manner which overcomes the limitations described above.